1. Field of the Invention
The present invention relates to a computer implemented method for designing a semiconductor integrated circuit and a semiconductor integrated circuit including a plurality of dummy patterns provided in a multi-level interconnect.
2. Description of the Related Art
Along with the miniaturization of semiconductor integrated circuits, a low dielectric constant film having a lower dielectric constant than a silicon oxide film (SiO2) has been adopted as an interlayer dielectric in a semiconductor integrated circuit. Recently, a practical use of a porous low dielectric constant film (porous-low-k film) having microscopic pores in a dielectric has been tried.
It has been found that the semiconductor integrated circuit including interlayer dielectric formed of the porous low k dielectric has poor mechanical and adhesion strength. Therefore, cracks and peeling between dielectrics may occur due to mechanical stresses during fabrication processes, such as chemical mechanical polish (CMP).
It is also known that the mechanical strength of the dielectric is decreased when the relative dielectric constant of the dielectric is decreased. Therefore, formulation of the semiconductor integrated circuit having a mechanical strength strong enough to endure mechanical stresses during fabrication has been needed in addition to the development of new materials of low k dielectrics.
To reinforce the mechanical strength of semiconductor integrated circuit, a semiconductor integrated circuit having a plurality of dummy patterns provided in part of an interconnection layers is known. However, when too many dummy patterns are inserted in one part of the interconnection layers, pattern density will be increased. Accordingly, the semiconductor integrated circuit having dummy patterns may fail to work due to crosstalk noise between adjoining patterns. Therefore, further miniaturization and integration of the semiconductor integrated circuit will become difficult.